1. Field
Exemplary embodiments of the present invention relate to an integrated circuit chip and a memory device having the same, and more particularly, to a technology of testing whether each pad (pin) of an integrated circuit chip is electrically connected to a substrate (board).
2. Description of the Related Art
When an integrated circuit chip such as a memory device is attached to a board, a test is performed to check a bonding state regarding whether bonding of a package is made and pins are connected to the board, in a desired manner. The conventional art uses a scheme of testing a bonding state of a board and pins using a test scheme called a boundary scan test. However, since this scheme performs a test by shifting a test pattern, a much longer test time may be required.
In a recent memory device, a connectivity test scheme of simultaneously applying signals to a plurality of pads of a chip and testing an electrical connection state of the pads in a parallel manner has been proposed. In this regard, a chip design of stably supporting a connectivity test of new scheme may be required.